1. Field of the Invention
The present invention relates to transistors and, more particularly, to power MOSFETs which are used in most power supply circuits and the like.
2. Description of the Related Art
Reference number 101 in FIGS. 43 and 44 represents a trench type power MOSFET according to the related art. FIG. 44 is a sectional view taken along the line C—C in FIG. 43.
As shown in FIG. 44, the power MOSFET 101 has a semiconductor substrate 105 provided by forming a drain layer 112 constituted by an n−-type epitaxial layer and p-type body regions 115 on an n+-type silicon substrate 111 sequentially. The power MOSFET 101 also has a plurality of cells 103 as shown in FIG. 43. The plurality of rectangular cells 103 is formed in a staggered configuration on a top surface of the semiconductor substrate 105. FIG. 43 shows six cells 1031 through 1036 and omits a source electrode film which will be described later.
As shown in FIG. 44, a trench 118 having a rectangular section whose bottom extends into the drain layer 112 is formed in the p-type body region 115 of each cell 103, and a p+-type diffusion region 124 extending to a predetermined depth from the top surface of the p-type body region 115 is formed in a position between adjacent trenches 118. An n+-type source region 127 extending to a depth short of the drain layer 112 from the surface of the p-type body region 115 is formed around the p+-type diffusion region 124 and around the opening of the trench.
A gate insulating film 119 is formed on the inner circumferential surface and the bottom surface of the trench 118, and a polysilicon gate 130 is formed on the surface of the gate insulating film 119 such that it fills the interior of the trench 118 and such that the upper end thereof is located higher than the lower end of the source region 127.
A PSG (phosphosilicate glass) film 128 is formed on top of the polysilicon gate 130, and a source electrode film 129 made of Al is formed to coat the top surfaces of the PSG film 128 and the semiconductor substrate 105. The polysilicon gate 130 and source electrode film 129 are electrically insulated by the PSG film 128.
In a power MOSFET 101 having such a structure, when a voltage equal to or higher than a threshold voltage is applied across the polysilicon gates 130 and the source electrode film 129 with a high voltage applied across the source electrode film 129 and drain layer 112, inversion layers are formed at interfaces between the gate oxide films 119 and p-type body regions, and a current flows from the drain to the source through the inversion layers.
In a power MOSFET 101 having the above-described structure, the PSG films 128 must be patterned using photolithography to provide direct contact between the source electrode film 129 and each of the source regions 127 on the top surfaces of the source regions 127. Since misalignment of the PSG films 128 can occur when they are formed using such a method, the area occupied by the PSG films 128 on the top surface of the semiconductor substrate 105 includes some margin to ensure insulation between the source electrode film 129 and polysilicon gates 130 even if there is some misalignment.
Consequently, the PSG films 128 are formed not only above the trench 118 but also around the openings of the trench.
The parts of the source regions 127 formed around the openings of the trench 118 are therefore located under the PSG films 128 and, in order to provide contact between the source electrode film 129 and the source regions 127 with a sufficiently low resistance, a large area of the source regions 127 must be exposed in advance on the top surface of the semiconductor substrate. As a result, the area occupied by the source regions 127 on the top surface of the semiconductor substrate 105 can not be reduced beyond a certain limit, and this has hindered efforts toward finer devices.